Features

• Bidirectional Buffer for SDA and SCL Lines Increases Fanout
• Prevents SDA and SCL Corruption During Live Board Insertion and Removal from Backplane
• Isolates Input SDA and SCL Lines from Output
• Compatible with I²C™, I²C Fast Mode and SMBus Standards (Up to 400kHz Operation)
• Low I_CCChip Disable:
• READY Open Drain Output (LTC4300-1)
• 1V Precharge on all SDA and SCL Lines
• Supports Clock Stretching, Arbitration and Synchronization
• 5V to 3.3V Level Translation (LTC4300-2)
• High Impedance SDA, SCL Pins for V_CC = 0V
• Small MSOP 8-Pin Package

Typical Application

Description

The LTC4300 series hot swappable 2-wire bus buffers allow I/O card insertion into a live backplane without corruption of the data and clock busses. When the connection is made, the LTC4300-1/LTC4300-2 provide bidirectional buffering, keeping the backplane and card capacitances isolated. Rise-time accelerator circuitry* allows the use of weaker DC pull-up currents while still meeting rise-time requirements. During insertion, the SDA and SCL lines are precharged to 1V to minimize bus disturbances.

The LTC4300-1 incorporates a CMOS threshold digital ENABLE input pin, which forces the part into a low current mode when driven to ground and sets normal operation when driven to V_CC. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. The LTC4300-2 replaces the ENABLE pin with a dedicated supply voltage pin, V_CC2, for the card side, providing level shifting between 3.3V and 5V systems. Both the backplane and card may be powered with supply voltages ranging from 2.7V to 5.5V, with no contraints on which supply voltage is higher. The LTC4300-2 also replaces the READY pin with a digital CMOS input pin, ACC, which enables and disables the rise-time accelerator currents.

The LTC4300 is available in a small 8-pin MSOP package.

*U.S. Patent No. 6,650,174