Features

• Sample Rate: 210Msps
• 65.5dB SNR
• 78dB SFDR
• 1.2GHz Full Power Bandwidth S/H
• Single 2.5V Supply
• Low Power Dissipation: 585mW
• LVDS, CMOS, or Demultiplexed CMOS Outputs
• Selectable Input Ranges: ±0.5V or ±1V
• No Missing Codes
• Optional Clock Duty Cycle Stabilizer
• Shutdown and Nap Modes
• Data Ready Output Clock
• Pin Compatible Family
  250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit)
  210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit)
  170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit)
  185Msps: LTC2220-1 (12-Bit)
  170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
  135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
• 64-Pin 9mm × 9mm QFN Package

Typical Application

Description

The LTC2241-12 is a 210Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2241-12 is perfect for demanding communications applications with AC performance that includes 65.5dB SNR and 78dB SFDR. Ultralow jitter of 95fsRMS allows IF undersampling with excellent noise performance.

DC specs include ±0.7LSB INL (typ), ±0.4LSB DNL (typ) and no missing codes over temperature.

The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 2.625V.

The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance over a wide range of clock duty cycles.